Optimizing galvanic pulse plating parameters to improve indium bump to bump bonding

機譯：優化電鍍脈沖電鍍參數以改善銦凸點到凸點的結合

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The plating characteristics of a commercially available indium plating solution are examined and optimized to help meet the increasing performance demands of integrated circuits requiring substantial numbers of electrical interconnections over large areas. Current fabrication techniques rely on evaporation of soft metals, such as indium, into lift-off resist profiles. This becomes increasingly difficult to accomplish as pitches decrease and aspect ratios increase. To minimize pixel dimensions and maximize the number of pixels per unit area, lithography and electrochemical deposition (ECD) of indium has been investigated. Pulse ECD offers the capability of improving large area uniformity ideal for large area device hybridization. Electrochemical experimentation into lithographically patterned molds allow for large areas of bumps to be fabricated for low temperature indium to indium bonds. The galvanic pulse profile, in conjunction with the bath configuration, determines the uniformity of the plated array. This pulse is manipulated to produce optimal properties for hybridizing arrays of aligned and bonded indium bumps. The physical properties of the indium bump arrays are examined using a white light interferometer, a SEM and tensile pull testing. This paper provides details from the electroplating processes as well as conclusions leading to optimized plating conditions.

機譯：對可商購的銦電鍍液的電鍍特性進行了檢查和優化，以幫助滿足日益增長的集成電路性能要求，這些集成電路要求在大面積上進行大量電氣互連。當前的制造技術依賴于諸如銦之類的軟金屬蒸發成剝離抗蝕劑輪廓。隨著間距減小和縱橫比增大，這變得越來越難以實現。為了最小化像素尺寸并最大化每單位面積的像素數量，已經研究了銦的光刻和電化學沉積（ECD）。脈沖ECD具有改善大面積均勻性的能力，非常適合大面積設備雜交。光刻圖案化模具中的電化學實驗可為低溫銦與銦鍵制造大面積的凸點。電脈沖輪廓與鍍液配置一起決定了鍍覆陣列的均勻性。操縱該脈沖以產生最佳性能，以使對準和鍵合的銦凸點陣列雜交。使用白光干涉儀，SEM和拉伸拉力測試檢查銦凸點陣列的物理性質。本文提供了電鍍工藝的詳細信息以及可優化電鍍條件的結論。

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來源
《Micromachining and microfabrication process technology XV》|2010年|P.75900F.1-75900F.11|共11頁
會議地點 San Francisco CA(US)
作者
Jonathan J. Coleman; rnAdam Rowen; rnSeethambal S. Mani; rnW. Graham Yelton; rnChristian Arlington; rnRusty Gillen; rnAndrew E. Hollowell; rnDaniel Okerlund; rnAdrian Ionescu;
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作者單位

Sandia National Laboratories, 1515 Eubank Blvd., Albuquerque, NM, USA;

rnSandia National Laboratories, 1515 Eubank Blvd., Albuquerque, NM, USA;

rnSandia National Laboratories, 1515 Eubank Blvd., Albuquerque, NM, USA;

rnSandia National Laboratories, 1515 Eubank Blvd., Albuquerque, NM, USA;

rnSandia National Laboratories, 1515 Eubank Blvd., Albuquerque, NM, USA;

rnSandia National Laboratories, 1515 Eubank Blvd., Albuquerque, NM, USA;

rnSandia National Laboratories, 1515 Eubank Blvd., Albuquerque, NM, USA;

rnDRS Technologies, Cypress, CA;

rnDRS Technologies, Cypress, CA;

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會議組織
原文格式 PDF
正文語種 eng
中圖分類微電子學、集成電路（IC）;
關鍵詞
electrodeposition; ECD; pulse; bump bond; indium; electroplating; electrochemistry;

機譯：電沉積ECD；脈沖;凹凸結合銦;電鍍;電化學;

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Optimizing galvanic pulse plating parameters to improve indium bump to bump bonding

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